Register $0 VIA Port B Input/Output

Bit 0 MUX Enable

This bit is responsible for enabling the multiplexer which selects where the Sample/Hold values the DAC at this time "produces" are switched to.

if set to 0 the multiplexer is ENABLED if set to 1 the multiplexer is DISABLED

Bit 1 and bit 2 Mux Select

These two bits are used together to build a 2 bit value. This two bit value ranges from 0 to 3. According to the resulting number, the multiplexer switches the output of the DAC to the respective recieving hardware:
0 (binary: 00) Integrator for vector y-position
1 (binary: 01) X, Y integrator offset values
2 (binary: 10) Z-value of vector hardware (brightness)
3 (binary: 11) audio hardware

Note:
The only known use of state 3 is the playing of samples, since this is a direct connection of the DAC value to the audio hardware... "Eek", "Help", "Spike"...

Note:
The same select lines are used to demultiplex the joystick analog potentiometers:
0 (binary: 00) port 0 horizontal
1 (binary: 01) port 0 vertical
2 (binary: 01) port 1 horizontal
3 (binary: 11) port 1 vertical

For more information regarding joystick input, see Joyport devices.

Bit 3 sound BC1 + Bit 4 sound BDIR

The above two bits are again "bundled" to 4 different possible states of communiction with the PSG chip:

  1. 0 (binary: 00) PSG Inactive
    The PSG/CPU bus is inactive DA7--DA0 are in high impedance state.

  2. 1 (binary: 01) Read from PSG
    This signal causes the contents of the register which is currently addressed to appear on the PSG/CPU bus. DA7--DA0 are in the output mode.

  3. 2 (binary: 10) Write to PSG
    This signal indicates that the bus contains register data which should be latched into the currently addressed register. DA7--DA0 are in the input mode.

  4. 3 (binary: 11) Latch address
    This signal indicates that the bus contains a register address which should be latched in the PSG. DA7--DA0 are in input mode.

Communication to any devices connected to the joyport is done via PSG. See ALSO Joyport devices for more information about accessing PSG chip.

Bit 5 comparator input

See Joyport devices ...

Bit 6 external device (slot pin 35) initialized to input

Communication with cartridge, -> Bankswitching, RAM, eEprom etc

Bit 7 /RAMP

The ramp bit controls the activity of the integrators. If RAMP is zero, the integrators are active. If RAMP is one the integrators are not active. Depending on the settings of the VIA auxiliary register this bit can be set by accessing bit 7 of port B - or is controlled by Timer T1.