With the auxilary control register the behaviors of the timers and the shift register can be configured (also latching for ORA and ORB, but I am not aware that this makes any since for vectrex).
SHIFT Mode is contolled by bit 2-4 with these 3 bits 8 SHIFT mode can be configured
The first mode is DISABLE. The next 3 modes are SHIFT IN modes, which is not used by vectrex.
The other four modes:
100 SHIFT out free running at T2 rate
101 SHIFT out under control of T2
110 SHIFT out under control of system clock
111 SHIFT out under control of ext clock
Usually shift mode is allways set to 110 - shift out under control of system clock.
Timer 1 modes (bit 7 and bit 6):
bit 7: 1x if set, on timer start ORB bit 7 goes LOW (RAMP = active), on timer stop, ORB bit 7 goes high (RAMP = not active)
10 One shot mode (timer runs till zero than stops)
11 continues mode (timer runs till zero than "reloads" latch and starts anew)
01 & 00 same as above without ORB bit 7
On normal vector draw bit 7 is usually set.
On normal "raster" draw bit 7 is often not set.
So you may see:
$18: T1 OneSHotMode WITHOUT Ramp control, Shift out under System clock
$98: T1 OneSHotMode WITH Ramp control, Shift out under System clock