In vectrex terms the shiftreg is one of the most important registers of VIA, since it can control the CB2 (~BLANK) line. The shift modes can be set with Reg $0b and are described there. Each time a shift "outputs" a bit that bit is placed into the CB2 line. Shifting out a 0 enables blank (light is switched off), each time a 1 is shifted out blank is disabled (light is switched on). The shift direction is: most significant bit first, the bit 7 is rotated back to position 0.
Shifting is done each 2 two processor cycles (shift out at system clock).
A complete Shift cycle takes 18 cycles, the last shifted value is held for an additional 2 cycles.
If a shift cycle is interrupted (a new shift initiated) VIA can stall (current shifted out value is held, no further shifting occurs). The time at which a stalling occurs appears to be dependend on the VIA generation. Known values (cycle counts) are 14 cycles and 15 cycles.
Attention:
The 6809 instruction CLR also READS the value befor it clears it, thus an instruction
CLR shiftreg
reads the shift register after 4 cycles and writes the shift register after an additional 2 cycles.
a shift is started by reading and by writing to the shiftreg