Sometimes people also say PIA (Periphal Interface Adapter, but that name usuall goes to another chip 6520), although since VIA is more "versatile" it includes all stuff PIA can do - and more!
VIA is accessed from Vectrex programs using 16 registers which are mapped to the memory location ranging from:
$d000 to $d00f
That mapping is shadowed 128 times in the following regions, that means VIA registers are mapped from $d000 to $d800.
For general 6522 description see elsewhere, here I will only collect vectrex relevant stuff.
This bit is responsible for enabling the multiplexer which selects where the Sample/Hold values the DAC at this time "produces" are switched to.
if set to 0 the multiplexer is ENABLED if set to 1 the multiplexer is DISABLED
These two bits are used together to build a 2 bit value. This two bit value ranges from 0 to 3. According to the resulting number, the multiplexer switches the output of the DAC to the respective recieving hardware:
0 (binary: 00) Integrator for vector y-position
1 (binary: 01) X, Y integrator offset values
2 (binary: 10) Z-value of vector hardware (brightness)
3 (binary: 11) audio hardware
Note:
The only known use of state 3 is the playing of samples, since this is a direct connection of the DAC value to the audio hardware... "Eek", "Help", "Spike"...
Note:
The same select lines are used to demultiplex the joystick analog potentiometers:
0 (binary: 00) port 0 horizontal
1 (binary: 01) port 0 vertical
2 (binary: 01) port 1 horizontal
3 (binary: 11) port 1 vertical
For more information regarding joystick input, see Joyport devices.
The above two bits are again "bundled" to 4 different possible states of communication with the PSG chip:
0 (binary: 00) PSG Inactive
The PSG/CPU bus is inactive DA7--DA0 are in high impedance state.
1 (binary: 01) Read from PSG
This signal causes the contents of the register which is currently addressed to appear on the PSG/CPU bus. DA7--DA0 are in the output mode.
2 (binary: 10) Write to PSG
This signal indicates that the bus contains register data which should be latched into the currently addressed register. DA7--DA0 are in the input mode.
3 (binary: 11) Latch address
This signal indicates that the bus contains a register address which should be latched in the PSG. DA7--DA0 are in input mode.
Communication to any devices connected to the joyport is done via PSG. See ALSO Joyport devices for more information about accessing PSG chip.
See Joyport devices ...
Communication with cartridge, → Bankswitching, RAM, eEprom etc
The ramp bit controls the activity of the integrators. If RAMP is zero, the integrators are active. If RAMP is one the integrators are not active. Depending on the settings of the VIA auxiliary register this bit can be set by accessing bit 7 of port B - or is controlled by Timer T1.
For vectrex purposes via port A is:
simply the digital register that serves as input to the Digital to Analog Converter (DAC).
if BC1 and BDIR are configured - the port that sends (receives from) data to the PSG
Port B can be used as an output register (referred to as ORB) or as an input register (referred to as IRB). The configuration for input and output can be set for each bit of the port. Usually all bits except bit 5 and 6 are configured as output. Bit 5 and 6 are configured as input.
Bit 6 is connected to the "external line" of the cartridge interface of the vectrex. Because of this bit 6 can be used to "communicate" with hardware "inside" cartridges.
Many multicards and other hardware use bit 6 for this purpose (see bankswitching).
The "tricky" thing with vectrex is, if PB6 is configured as input, bit 6 goes automatically high. If set to output it goes to low automatically. Even if in output mode and a "ONE" is written to pb6, it only goes high for a short period of time and than switches back to low automatically.
In vectrex terms the shiftreg is one of the most important registers of VIA, since it can control the CB2 (~BLANK) line. The shift modes can be set with Reg $0b and are described there. Each time a shift "outputs" a bit that bit is placed into the CB2 line. Shifting out a 0 enables blank (light is switched off), each time a 1 is shifted out blank is disabled (light is switched on). The shift direction is: most significant bit first, the bit 7 is rotated back to position 0.
Shifting is done each 2 two processor cycles (shift out at system clock).
A complete Shift cycle takes 18 cycles, the last shifted value is held for an additional 2 cycles.
If a shift cycle is interrupted (a new shift initiated) VIA can stall (current shifted out value is held, no further shifting occurs). The time at which a stalling occurs appears to be dependend on the VIA generation. Known values (cycle counts) are 14 cycles and 15 cycles.
Attention:
The 6809 instruction CLR also READS the value befor it clears it, thus an instruction
CLR shiftreg
reads the shift register after 4 cycles and writes the shift register after an additional 2 cycles.
a shift is started by reading and by writing to the shiftreg
Note:
Why 18 cycles and 9 shifts?
This is because (most) VIA ships (all vectrex used ships to my knowledge) have a bug.
When shifting using Phi2 (System clock) [Mode 110, see below], VIA outputs 9 shift pulses, the last shifted value is repeated.
[See: Synertek sy6522 Applications Information AN5 March 1982]
With the auxilary control register the behaviors of the timers and the shift register can be configured (also latching for ORA and ORB, but I am not aware that this makes any sense for vectrex).
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
|___T1__|T2_|___SHIFT___|PB_|PA_|
SHIFT Mode is contolled by bit 2-4 with these 3 bits 8 SHIFT mode can be configured
The first mode is DISABLE. The next 3 modes are SHIFT IN modes, which is not used by vectrex.
The other four modes:
100 SHIFT out free running at T2 rate
101 SHIFT out under control of T2
110 SHIFT out under control of system clock
111 SHIFT out under control of ext clock
Usually shift mode is allways set to 110 - shift out under control of system clock.
Timer 1 modes (bit 7 and bit 6):
bit 7: 1x if set, on timer start ORB bit 7 goes LOW (RAMP = active), on timer stop, ORB bit 7 goes high (RAMP = not active)
10 One shot mode (timer runs till zero than stops)
11 continues mode (timer runs till zero than "reloads" latch and starts anew)
01 & 00 same as above without ORB bit 7
On normal vector draw bit 7 is usually set.
On normal "raster" draw bit 7 is often not set.
So you may see:
$18: T1 OneSHotMode WITHOUT Ramp control, Shift out under System clock
$98: T1 OneSHotMode WITH Ramp control, Shift out under System clock
VIA Control register "controls" the Control lines of via. Control lines are:
CA1
CA2
CB1
CB2
All control lines act as interrupt inputs or as handshake Outputs.
+---+---+---+---+---+---+---+---+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+
|____CB2____|CB1|____CA2____|CA1|
For vectrex anlog parts (and for now) the lines CA2 (ZERO) and CB2 (BLANK) are most interesting.
CA1
The CA1 line is connected to the second joystickport of the vectrex, more specific to button4. For joystick activity the controlline is not used. However, the lightpen device and the 3d Imager make use of that control line!
The lightpen for example "triggers" CA1 when it sees some "light" :-). Bit 0 controls the interrupt behaviour of the CA1 line. Usually the bit is (left ) to 0. If this bit is a logic 0, the CAl interrupt flag will be set by a negative transition (high to low) of the signal on the CAl pin. If bit 0 is a logic 1, the CAl interrupt flag will be set by a positive transition (low to high) of this signal. The Imager 3d (at least in Narrow Escape), sets this bit to 1 to receive the "signal" from the index hole.
CA2 - ZERO
Responsible bits are bit 1-3:
110 = LOW output (translated to vectrex analog - ZERO is enabled)
111 = HIGH output (translated to vectrex analog - ZERO is diaabled)
CB2 - BLANK
Responsible bits are bit 5-7:
110 = LOW output (translated to vectrex analog - BLANK is enabled)
111 = HIGH output (translated to vectrex analog - BLANK is diaabled) Although blank is "usually" controlled by the shift register (output)!
Together in vectrex terms:
(assuming bit 0 and 5 (interrupt controls for CA1 and CB1) are zero)
%110x110x = $cc means ZERO enabled, and BLANK enabled
%111x110x = $ec means ZERO enabled, and BLANK disabled
%111x111x = $ee means ZERO disabled, and BLANK disabled
%110x111x = $ce means ZERO disabled, and BLANK enabled
Note:
The manual appliance to the BLANK singnal with the control register only has any effect if SHIFT is switched to OFF.
Write one to a bit resets the interrupt flag.
0x01 : bit 0 CA2 interrupt (cleared by read/write port A depeneding on "independed" interrupt)
0x02 : bit 1 CA1 interrupt (edge is determined by PCR bit 0, cleared by read/write of Port A)
0x04 : bit 2 Shiftreg interrupt (complete 8 shifts)
0x08 : bit 3 CB2 interrupt
0x10 : bit 4 CB1 interrupt
0x20 : bit 5 Timer2 interrupt
0x40 : bit 6 Timer1 interrupt
0x80 : bit 7 indicates whether ANY interrupt happened
if bit 7 is 1
0 interrupt disabled
1 interrupt enabled
if bit 7 is 0
1 interrupt disabled
0 interrupt enabled
0x01 : bit 0 CA2 interrupt
0x02 : bit 1 CA1 interrupt
0x04 : bit 2 Shiftreg interrupt
0x08 : bit 3 CB2 interrupt
0x10 : bit 4 CB1 interrupt
0x20 : bit 5 Timer2 interrupt
0x40 : bit 6 Timer1 interrupt
0x80 : bit 7 indicates whether ANY interrupt happened
VIA has two timers, both are "used" by the vectrex. How these timer exactly operate → see Manual of VIA.
Timer operations are controlled by the AUXILIARY Control register ($b). The timer relevant bits are:
Timer 1: bit 6-7
Timer 2: bit 5
The "usual" setting for the timers is:
Timer 1: 10 (One Shot Mode, Timed interrupt each time T1 is loaded)
Timer 2: 0 (Timed interrupt)
Timer 1 is usally used to move the beam across the vectrex screen. Both for just "moving" and "drawing" (only difference is, whether the light of the beam is switched on or off).
For this the timer 1 is configured to the so called "one Shot Mode" ("timing stops after the coundown finished).
Note:
Timer starts when something is written to the high byte. So you usually see something like "clr t1h", when timing starts.
Using Timer 1 in one shot mode has one neat effect, the 7 bit of VIA ORB is "automatically" set to LOW when the timer starts (clr t1h), and "automatically" set to "HIGH" when the timer is finished. Bit 7 of ORB is the analog equivalent to RAMP. Setting PB7 to low means enabling RAMP, and setting it to high means disabling RAMP.
Using Timer 1 in combination with its ability to directly "control" the analog integrators makes it just about "perfect" to draw vectors for vectrex!
In vectrex Timer 1 (low value) is usually reffered to as "the scale" of a vector.
Is used to track "system" time, and wait for 50Hz to be reached and than to do a recalibration (30.000 cycles). This value can be set to vectrex ram: